A readout integrated circuit has been designed in order to realize digital output of the IRFPA, which includes an 8×1 ROIC unit cell array and a 10 bit successive approximation analogtodigital converter. The input stage of the unit cell is capacitive transimpedance amplifier, whose output is transmitted to the analogtodigital converter by a multiplexer after sampleandhold. The comparator of the ADC is based on a twostage openloop comparator, and the digitaltoanalog converter is based on a DAC that uses charge scaling subDAC for the MSBs and voltage scaling subDAC for the LSBs. The circuit was simulated and the layout was designed using 0.6μm doublepoly, doublemetal CMOS technology under the Cadence full custom design platform. The power consumption of the whole chip is about 5mW at a 20 kHz conversion rate from a 5V supply.