The pixel level fusion of multicolor focal plane array detectors is realized on basis of high performance and low power consumption of micro image fusion system. A SoPC (System on a Programmable Chip) level dualchannel image fusion system is proposed in this paper based on Xilinx Virtex4 series FPGA. Modular design method is used in this SoPC system, which consists of functional modules including image acquisition, nonuniformity correction preprocessing, fusion and output, etc. according to the processing flow. This system can make full use of the advanced features of the device to insure realtime processing. According to the simulation results, the feasibility of the SoPC level dualchannel 720×576×10bit image fusion system is analyzed concerning the algorithm selection, the computational complexity, the resource occupation of the design. At last, the power consumption of the SoPC system and the ASIC deriving from the SoPC are estimated as well.